Methods of patterning dielectric layers for metallization and related structures

ABSTRACT

Structures including metallization layers and metal lines, and methods of forming thereof. A patterning stack, a masking layer, and a spacer patterning layer are formed over a dielectric layer, and an opening is formed in the spacer patterning layer. First and second spacers are formed on a portion of the masking layer at sidewalls of an opening in the spacer patterning layer. The first spacer and the second spacer overlie and traverse first portions of the dummy line. After removing the spacer patterning layer and masking layer, second portions of the dummy line are removed to form a feature in the patterning stack that includes a first gap beneath the first spacer and a second gap beneath the second spacer. A metal line is formed in the dielectric layer using the feature, and includes cuts at the first gap and the second gap in the feature.

BACKGROUND

The present invention relates to semiconductor device fabrication andintegrated circuits and, more specifically, to methods of patterningdielectric layers for metal line formation and fabrication ofmetallization layers integrated circuits.

Metallization layers in integrated circuits allow for electricalconnection between layers of integrated circuits and external devices.As circuit sizes have continued to shrink, new methods for patterningmetallization layers and forming metallization lines continue to bedeveloped to overcome limitations of existing fabrication equipment inmeeting design requirements for newer and even smaller metal linefeatures.

SUMMARY

In an embodiment of the invention, a method includes forming apatterning stack over a dielectric layer, forming a masking layer overthe patterning stack and a spacer patterning layer over the maskinglayer, and etching an opening in the spacer patterning layer to expose aportion of the masking layer overlying a dummy line of the patterningstack. The method further includes forming a first spacer and a secondspacer on the exposed portion of the masking layer at sidewalls of theopening. The first spacer and the second spacer overlie and traverserespective first portions of the dummy line. The method further includesremoving the spacer patterning layer and the masking layer selective tothe patterning stack, the first spacer, and the second spacer to exposesecond portions of the dummy line, and removing the second portions ofthe dummy line selective to the first spacer and the second spacer toform a feature in the patterning stack that includes a first gap beneaththe first spacer and a second gap beneath the second spacer. A metalline is formed in the dielectric layer using the feature in thepatterning stack. The metal line includes respective cuts at the firstgap and the second gap in the feature in the patterning stack.

In another embodiment of the invention, a structure includes a firstmetallization layer including a plurality of first metal lines and ametal island, a second metallization layer including a second metal linearranged or disposed below the first metallization layer, and a thirdmetallization layer including a third metal line arranged or disposedabove the first metallization layer. A first conductive via connects themetal island to the second metal line and a second conductive viaconnects the metal island to the third metal line. The first conductivevia, second conductive via, and metal island provide electricalconnectivity between the second metal line and third metal line.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate various embodiments of theinvention and, together with a general description of the inventiongiven above and the detailed description of the embodiments given below,serve to explain the embodiments of the invention.

FIGS. 1-10 are cross-sectional views of a structure at successivefabrication stages of a processing method in accordance with embodimentsof the invention.

FIG. 1A is a top view of the structure in which FIG. 1 is takengenerally along line 1-1.

FIG. 3A is a top view of the structure in which FIG. 3 is takengenerally along line 3-3.

FIG. 6A is a top view of the structure in which FIG. 6 is takengenerally along line 6-6.

FIG. 7A is a top view of the structure in which FIG. 7 is takengenerally along line 7-7.

FIG. 8A is a top view of the structure in which FIG. 8 is takengenerally along line 8-8.

FIG. 9A is a top view of the structure in which FIG. 9 is takengenerally along line 9-9.

FIG. 10A is a top view of the structure in which FIG. 10 is takengenerally along line 10-10.

FIG. 11 is a cross-sectional view of a structure at an alternativefabrication stage following FIG. 6 of a processing method in accordancewith embodiments of the invention.

FIG. 11A is a top view of the structure in which FIG. 11 is takengenerally along line 11-11.

FIGS. 12 and 13 are cross-sectional views of the structure of FIGS. 1-10at further fabrication stages of a processing method in accordance withembodiments of the invention.

DETAILED DESCRIPTION

With reference to FIGS. 1 and 1A and in accordance with embodiments ofthe invention, a structure 100 includes one or more lower circuitstructure layers 105, a dielectric layer 110, and a patterning stack 120that includes a hardmask layer 122, a dielectric layer 124, and dummylines 125, 126. Dummy lines 125, 126 may be formed by a lithography andetch process from a deposited layer of its material. Dummy lines 125,126, which may be composed of a sacrificial material, such as amorphoussilicon (a-Si), are embedded in the dielectric layer 124. Dummy lines126 are patterned with large tip-to-tip spacings.

Dielectric layer 124 may be composed of, for example, silicon dioxidedeposited by plasma-enhanced chemical vapor deposition (PECVD) on thehardmask layer 122 and over the dummy lines 125, 126, and then polishedto exposed the dummy lines 125, 126 at the top surface of the dielectriclayer 124. Hardmask layer 122 may be composed, for example, of titaniumnitride, titanium oxide, or other hardmask material. Dielectric layer110 may be composed of a dielectric material, such as an oxide ofsilicon or a nitride of silicon, in which metallization lines are to bepatterned using patterning stack 120, as described in part below.

With reference to FIG. 2 in which like reference numerals refer to likefeatures in FIGS. 1 and 1A and at a subsequent fabrication stage of theprocessing method, a masking layer 130 and a spacer patterning layer 135are formed over the patterning stack 120. Masking layer 130 may becomposed of a dielectric material, such as a nitride-based dielectricmaterial, and spacer patterning layer 135 may be composed of a differentdielectric material from masking layer 130, such as an oxide-baseddielectric material, so that masking layer 130 and spacer patterninglayer 135 have differing etch selectivity properties. For example,masking layer 130 may be composed of silicon nitride and spacerpatterning layer 135 may be composed of silicon dioxide. Spacerpatterning layer 135 may be formed to a selected thickness T₁ that may,in part, facilitate formation of spacers as described further below.Masking layer 130 may have a thickness T₂ that is less than thethickness T₁ of spacer patterning layer 135. The thickness T₁ of spacerpatterning layer 135 may, as described below, partially define a heightof spacers 151 and 152 formed on sidewalls of an opening 137 (FIG. 4)patterned in the spacer patterning layer 135.

With reference to FIGS. 3 and 3A and in which like reference numeralsrefer to like features in FIG. 2 and at a subsequent fabrication stageof the processing method, a lithography stack 140 and a resist layer 144are formed over spacer patterning layer 135. Lithography stack 140 mayinclude an organic spin-on hardmask (SOH) layer, a silicon oxynitride(SiON) hardmask layer, and an anti-reflective coating layer. The resistlayer 144 is patterned to form an opening 145, or multiple openings asdescribed below, aligned over portions of dummy line 125 that isdesignated to be cut to provide small tip-to-tip spacings. The opening145 exposes a portion of spacer patterning layer 135 to be etched andremoved as described below.

With reference to FIG. 4 in which like reference numerals refer to likefeatures in FIGS. 3 and 3A and at a subsequent fabrication stage of theprocessing method, an opening 137 is etched in spacer patterning layer135. Opening 137 may be formed, for example, by a reactive ion etch (ME)process. The opening 137 may have a width dimension W that is aboutequal to twice a selected thickness T₃ of a conformal layer 150 to beformed over spacer patterning layer 135 plus a length L separating aspacer 151 from a spacer 152 (which are formed from conformal layer 150)as shown in FIG. 5. For example, selected thickness T₃ of conformallayer 150 may be about 5 nm, and length L separating spacers 151 and 152may be about 15 nm, so that width W of opening 137 may be about 25 nm.The etching may be a selective etch process that is controlled to removethe exposed portion of spacer patterning layer 135 and to terminate onthe material of the masking layer 130. The opening 137 exposes a portionof masking layer 130 overlying a portion of dummy line 125. As usedherein, the term “selective” in reference to a material removal process(e.g., etching) denotes that, with an appropriate etchant choice, thematerial removal rate (i.e., etch rate) for the targeted material isgreater than the removal rate for at least another material exposed tothe material removal process.

The opening 137, which is a single opening of relatively largedimensions in the spacer patterning layer 135, may be used to formmultiple closely-spaced cuts, as subsequently described, in contrastwith conventional techniques that require multiple “colors” or stages ofpatterning to form closely-spaced cuts of small relative dimensions. Inaddition, the spacing between adjacent conventional cuts may be limiteddue to lithography resolution limits, which is mitigated through the useof spacers as described below.

With reference to FIG. 5 in which like reference numerals refer to likefeatures in FIG. 4 and at a subsequent fabrication stage of theprocessing method, a conformal layer 150 is deposited on the spacerpatterning layer 135 and over the sidewalls and base of the opening 137in spacer patterning layer 135. The sections of conformal layer 150deposited on sidewalls of opening 137 define a spacer 151 and a spacer152. As depicted and described below in FIG. 6A, spacer 151 and spacer152 may be included among a plurality of spacers that are arranged toform a “spacer ring” 155 on the sidewalls of the opening 137. As alsodescribed and depicted below in FIG. 6A, spacer 151 and spacer 152overlie and traverse dummy line 125. The thickness T₁ of spacerpatterning layer 135 may define, at least in part, a height of spacers151 and 152 formed on sidewalls of the opening 137 of spacer patterninglayer 135. The thickness T₃ of the conformal layer 150 may be selectedto determine a thickness T₄ of spacers 151 and 152 and may furtherdefine, at least partially, a length L separating spacer 151 and spacer152. The thickness T₄ of spacer 151 and of spacer 152 may also define asize of gaps separating ends of metal lines formed in dielectric layer110, as described further below. For example, a conformal layer 150having a thickness T₃ of 5 nm may form spacers 151, 152 having thicknessT₄ of 5 nm, so that gaps formed between the ends of metal lines indielectric layer 110 are also 5 nm. The length L separating spacer 151and spacer 152 may be 15 nm or less, so that a resulting metal island165 formed in dielectric layer 110, as described further below, may havea length L_(m) of 15 nm or less. The conformal layer 150, and byextension, the spacers 151 and 152, and masking layer 130 may becomposed of the same material, for example a nitride-based dielectricmaterial such as silicon nitride.

With reference to FIGS. 6 and 6A in which like reference numerals referto like features in FIG. 5 and at a subsequent fabrication stage of theprocessing method, conformal layer 150 is removed from over spacerpatterning layer 135, leaving spacer ring 155, including spacer 151 andspacer 152, disposed over the exposed portion of masking layer 130. Theconformal layer 150 may be removed, for example, by a selectiveanisotropic etch process, such as a reactive-ion etch (RIE) process,controlled to terminate when spacer patterning layer 135 is exposed bythe etch. A controlled anisotropic etch process allows for removal ofthe conformal layer 150 with minimal etching of spacers 151, 152. AsFIG. 6A illustrates, the conformal layer 150 deposited on sidewalls ofthe opening 137 in spacer patterning layer 135 may form the spacer ring155 or ring-like spacer formation, including the spacer 151 and spacer152 that overlie and traverse dummy line 125.

With reference to FIGS. 7 and 7A in which like reference numerals referto like features in FIGS. 6 and 6A and at a subsequent fabrication stageof the processing method, spacer patterning layer 135 and masking layer130 are removed, which leaves spacers 151 and 152 disposed overdifferent sections of the dummy line 125. As FIGS. 7 and 7A show, spacer151 and spacer 152 overly and traverse dummy line 125 in a spaced apartfashion. Spacer patterning layer 135 may be removed by a selective etchprocess that selectively removes the material of spacer patterning layer135 without etching either the masking layer 130 or spacers 151, 152.Masking layer 130 may be etched by a selective etch process controlledto remove masking layer 130 without fully etching or removing spacer 151and spacer 152, such as a reactive ion etching (RIE) process controlledto terminate when the dielectric layer 124 of patterning stack 120 isexposed by the etch process.

With reference to FIGS. 8 and 8A in which like reference numerals referto like features in FIGS. 7 and 7A and at a subsequent fabrication stageof the processing method, dummy lines 125 and 126 are removed to exposeunderlying portions of hardmask layer 122. Spacer 151 and spacer 152protect underlying portions 127, 128 of dummy line 125 from removal, sothat in subsequent fabrication stages, as described below, the portionsof hardmask layer 122 underlying the remaining portions 127, 128 ofdummy line 125 will remain unetched and form “cuts” or gaps in a finalmetallization line to be formed in dielectric layer 110.

With reference to FIGS. 9 and 9A in which like reference numerals referto like features in FIGS. 8 and 8A and at a subsequent fabrication stageof the processing method, the exposed portions of hardmask layer 122 areetched to form trenches in the hardmask layer 122 and expose portions ofthe dielectric layer 110 to be etched. Remaining portions of spacers 151and 152 are also removed. The material of spacers 151 and 152, as wellas other spacers of spacer ring 155, may be removed by, for example, aselective etch process. Dielectric layer 124 may be removed via aseparate selective etch process, as illustrated in FIG. 9.Alternatively, dielectric layer 124 may remain to be etched during asubsequent etch of dielectric 110, illustrated in FIG. 10 and furtherdescribed below. Remaining portions 127, 128 of dummy line 125 protectthe underlying portions 122 a, 122 b of hardmask layer 122 and definegaps in the trenches formed in hardmask layer 122. Dummy lines 125, 126may be removed, for example, by a selective anisotropic etch processsuch as a reactive ion etching (RIE) process.

With reference to FIGS. 10 and 10A in which like reference numeralsrefer to like features in FIGS. 9 and 9A and at a subsequent fabricationstage of the processing method, metallization trenches are formed indielectric layer 110 using the trenches etched in hardmask layer 122,and the trenches are filled with a conductive material to form metallines 160, 161. Remaining portions of the hardmask layer 122 areremoved, exposing the dielectric layer 110. Metal line 165, resultingfrom the cuts or gaps defined by the spacers 151 and 152 as describedabove, may be considered a “metal island” as it is electrically isolatedfrom surrounding metal lines 160, 161. The metal island 165 may have alength L_(m) of 15 nm or less. The conductive material may be anyconductive material, such as cobalt or ruthenium or copper or otherconductive material used to form metal lines in a circuit structure.Cobalt may be a preferred conductive material for forming metal lines160, 161 and metal island 165 because cobalt may be used to form veryshort metal lines, such as metal islands of 15 nm or less, whereascopper metal lines generally must have a minimum length that is greaterthan 15 nm due to the material properties of copper and due toreliability issues during service and use of an integrated circuitstructure.

With reference to FIGS. 11 and 11A in which like reference numeralsrefer to like features in FIGS. 7 and 7A in a further embodiment of theprocessing method, multiple sets of spacers 156, 157, 158 may be formedover dummy line 125 to define multiple sets of cuts or gaps in the dummyline 125, and subsequently in metal lines formed in dielectric layer110. Multiple sets of spacers 156, 157, 158 may be formed via alithographic etch process, as described in part above, in which multipleopenings are etched in spacer patterning layer 135 and the conformallayer 150 subsequently deposited over spacer patterning layer 135 formsmultiple spacers 156, 157, 158. In embodiments in which an even numberof cuts or gaps are needed in dummy line 125, multiple wider openings,similar to opening 137 in spacer patterning layer 135 depicted in FIGS.4-5, may be formed in spacer patterning layer 135 that result in theformation of multiple spacer rings or ring-like spacers similar to thesingle spacer ring illustrated in FIGS. 5-6A. In embodiments in which anodd number of cuts or gaps in dummy line 125 are needed, multiple wideropenings, similar to opening 137 in spacer patterning layer 135 depictedin FIGS. 4-5, may be formed in spacer patterning layer 135 that resultin the formation of multiple spacer rings, and an additional narrowopening may be formed in spacer patterning layer 135 that results inspacers 158. The additional narrow opening in spacer patterning layer135 may have a width dimension W_(N) that is less than twice thethickness T₃ of the conformal layer 150 formed over the spacerpatterning layer 135, resulting in spacers 158 that merge into a singlespacer block disposed over dummy line 125. The single spacer blockformed by spacers 158 then forms a single cut or gap in dummy line 125.

With reference to FIGS. 12 and 13 in which like reference numerals referto like features in FIGS. 1-10A and in a further embodiment of theprocessing method, the dielectric layer 110, including metal lines 160,161, and metal island 165, may be one metallization layer in a circuitstructure 100a and may be disposed above a lower metallization layer 170having a plurality of metal lines 171 and below an upper metallizationlayer 175 having a plurality of metal lines 176. As depicted in FIG. 12,a lower metallization layer 170 may be formed first and a via 182 formedto connect to one metal line 171 in lower metallization layer 170. Thedielectric layer 110 may then be formed, as described above, with ametal island 165 aligned with the via 182 connected to metal line 171.Conductive via 182 may be formed, for example, by etching a hole throughthe dielectric material of dielectric layer 110, prior to formation ofmetal lines 160, 161, and metal island 165, and subsequently filling thehole with a conductive material such as cobalt, ruthenium, or copper.The conductive via 182 may be filled along with metal lines 160, 161,and metal island 165 in the same processing step or may be filled priorto forming metal lines 160, 161, and metal island 165 as describedabove. As depicted in FIG. 13, another conductive via 184 may then beformed that connects to metal island 165, and the upper metallizationlayer 175 may then be formed over dielectric layer 110 with one metalline 176 in upper metallization layer 175 aligned to and connecting withthe other conductive via 184. Conductive via 184 may be formed bysimilar processes as for forming via 182. The circuit structure 100aformed thus has an interconnection between upper metallization layer 175and lower metallization layer 170, wherein dielectric layer 110separates the upper metallization layer 175 and lower metallizationlayer 170. Conductive vias 182 and 184, in conjunction with metal island165 formed in dielectric layer 110, form an extended via or “super via”that permits interconnection between metal lines of non-adjacentmetallization levels in circuit structure 100a. The metal island 165formed as described herein allows for efficient conductive connectionbetween conductive vias 182 and 184 as metal island 165 may be formed tohave a size substantially equal to a size of conductive vias 182 and 184so as to minimize area losses.

The methods as described above are used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (e.g., as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case, the chip is mounted in a single chip package (e.g., aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (e.g., a ceramic carrierthat has either or both surface interconnections or buriedinterconnections). In any case, the chip may be integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either an intermediate product or an end product.

References herein to terms such as “vertical”, “horizontal”, “lateral”,etc. are made by way of example, and not by way of limitation, toestablish a frame of reference. Terms such as “horizontal” and “lateral”refer to a direction in a plane parallel to a top surface of asemiconductor substrate, regardless of its actual three-dimensionalspatial orientation. Terms such as “vertical” and “normal” refer to adirection perpendicular to the “horizontal” and “lateral” direction.Terms such as “above” and “below” indicate positioning of elements orstructures relative to each other and/or to the top surface of thesemiconductor substrate as opposed to relative elevation.

A feature “connected” or “coupled” to or with another element may bedirectly connected or coupled to the other element or, instead, one ormore intervening elements may be present. A feature may be “directlyconnected” or “directly coupled” to another element if interveningelements are absent. A feature may be “indirectly connected” or“indirectly coupled” to another element if at least one interveningelement is present.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

What is claimed is:
 1. A structure comprising: a first metallization layer comprising a plurality of first metal lines and a metal island, the metal island electrically isolated from the plurality of first metal lines; a second metallization layer disposed below the first metallization layer, the second metallization layer including a second metal line; a third metallization layer disposed above the first metallization layer, the third metallization layer including a third metal line; a first conductive via connecting the metal island to the second metal line; and a second conductive via connecting the metal island to the third metal line.
 2. The structure of claim 1 wherein the metal island has a length of less than or equal to fifteen nm.
 3. The structure of claim 1 wherein the metal island is comprised of cobalt or ruthenium.
 4. The structure of claim 1 wherein the metal island is comprised of cobalt.
 5. The structure of claim 1 wherein the metal island, the first conductive via, and the second conductive via are comprised of the same material.
 6. The structure of claim 1 wherein the first metallization level includes a fourth metal line arranged adjacent to the first metal line, and the fourth metal line is spaced from the first metal line by a first gap with a dimension of about five nm.
 7. The structure of claim 6 wherein the metal island has a length of less than or equal to fifteen nm.
 8. The structure of claim 6 wherein the first metallization level includes a fifth metal line arranged adjacent to the first metal line, the first metal line is laterally arranged between the fourth metal line and the fifth metal line, and the fifth metal line is spaced from the first metal line by a second gap with a dimension of about five nm.
 9. The structure of claim 8 wherein the metal island has a length of less than or equal to fifteen nm.
 10. The structure of claim 6 wherein the metal island and the fourth metal line are comprised of cobalt.
 11. The structure of claim 6 wherein the metal island, the fourth metal line, the first conductive via, and the second conductive via are comprised of the same material.
 12. The structure of claim 6 wherein the first metallization level includes a dielectric layer, and the gap is filled by dielectric material of the dielectric layer.
 13. The structure of claim 1 wherein the metal island is substantially equal in size to the first conductive via.
 14. The structure of claim 1 wherein the metal island is substantially equal in size to the second conductive via.
 15. The structure of claim 1 wherein the metal island is substantially equal in size to the first conductive via, and the metal island is substantially equal in size to the second conductive via.
 16. A structure comprising: a first metallization layer comprising a plurality of first metal lines and a metal island, the metal island electrically isolated from the plurality of first metal lines; a second metallization layer disposed below the first metallization layer, the second metallization layer including a second metal line; a third metallization layer disposed above the first metallization layer, the third metallization layer including a third metal line; a first conductive via connecting the metal island to the second metal line; and a second conductive via connecting the metal island to the third metal line, wherein the metal island is comprised of cobalt, the metal island has a length of less than or equal to fifteen nm, and the metal island is comprised of cobalt, and the metal island is substantially equal in size to the first conductive via.
 17. The structure of claim 16 wherein the first metallization level includes a fourth metal line arranged adjacent to the first metal line, and the fourth metal line is spaced from the first metal line by a first gap with a dimension of about five nm.
 18. The structure of claim 17 wherein the first metallization level includes a fifth metal line arranged adjacent to the first metal line, the first metal line is laterally arranged between the fourth metal line and the fifth metal line, and the fifth metal line is spaced from the first metal line by a second gap with a dimension of about five nm.
 19. The structure of claim 16 wherein the metal island is substantially equal in size to the second conductive via.
 20. The structure of claim 16 wherein the first metallization level includes a dielectric layer, and the gap is filled by dielectric material of the dielectric layer. 